The present invention relates, in general, to the field of compensating circuits and methods for stabilization of a circuit node in an integrated circuit by multiplication of junction capacitance displacement current. More particularly, the present invention relates to a compensation circuit and method which multiplies junction capacitance displacement current to provide stabilization of a sensitive circuit node which might otherwise oscillate due to capacitive coupling of the substrate when used as an output in certain integrated circuit technologies.
In the utilization of an N type epitaxial layer or well in conjunction with a P+ substrate and isolation regions, a diode exists at the junctions between the epitaxial layer and the substrate/isolation regions. Moreover, these junctions exhibit an associated parasitic capacitance, or junction capacitance.
This junction capacitance can create problems with many newer technology integrated circuits which take advantage of large output devices utilizing the substrate as an output terminal. Exemplary of such new devices are power vertical PNPs as well as bottom collector NPNs and CMOS/TMOS.TM. devices. These new technologies are currently being developed by numerous semiconductor manufacturers, including Motorola Inc., assignee of the present invention and owner of the trademark TMOS.
In the utilization of such "bottom technology" devices, when the output, taken at the substrate, swings rapidly, large displacement currents may flow through the parasitic capacitance associated with the junction isolation. Such circuits may therefore become extremely susceptible to this capacitive current. In such instances, the output of the device, rather than turning off at the appropriate time may oscillate between the supply voltage level, V.sub.CC and circuit ground due to induced displacement current at a sensitive circuit node in the device control circuitry.